ASIC设计工程师-NPU & AI
1. ADAS algorithm study and provide implement solution.
2. NPU micro architecture design according to PRD;
3. NPU micro architecture analysis, optimization and simulation.
4. NPU performance/power simulation and optimization.
5. NPU IP integration design and RTL coding;
6. NPU clock/reset architecture design, clock jitter assessment for high speed interface.
7. NPU low power architecture design.
8. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation;
9. Perform RTL-to-Netlist implementation using in-house implementation flow;
10. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.
11. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification；
12. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation；
1. Hand on experience of logic design；
2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools；
3. Familiar with scripts (tcl, perl, makefile etc.)
4. Experience of NPU design is a plus；
5. Experience of ADAS algorithm is a plus;
6. Experience of NPU performance optimization is a plus;
7. Experience of clock/reset design is a plus;
8. Experience of low power design is a plus; be familiar with DVFS and power gating.
9. Experience of Fusa design is a plus；
10. Teamwork, A high-level of self-motivation and a proactive approach to solving problems；